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    A reconfigurable multiprocessor system including a number of processing units and components enabling executing sequential code collectively at processing units and enabling changing the architectural configuration of the processing units.a plurality of processor units, wherein the plurality of processor units are independent cores and dynamically fused into a single processor, wherein the single processor is dynamically split into distinct processing units at run time; andat least one cross unit connection component operatively connecting at least two processor units from said plurality of processor units, said at least one cross unit connection component reconfigurably linking one processor unit to another processor unit, thereby fusing them as a single processor, said reconfigurable linking adjusting processing to sequential when in a fused mode and to parallel when in a split mode; said at least one cross unit connection component enabling collective fetching and providing instructions to be executed collectively by said at least two processor units and collectively committing executed instructions by said at least two processor units; said collective fetching comprising cooperatively fetching an instruction block; said instruction block comprising a number of subsets, said fetching being performed cooperatively by fetching a one subset of said instruction block by each of said at least two processor units, when the processor units are in the fused mode; said instruction block comprising each subsets of instructions fetched by each of said at least two processor units; said instruction block being constructed from each subset of instructions fetched by each of said at least two processor units; said collective fetching enabling operation of said at least two processor units substantially as a single processor unit; whereby executing sequential code collectively at processor units is enabled; andwhen changing manner of processing from fused to split or from split to fused, bringing an internal state of said plurality of processing units to a form consistent with a new configuration, resulting from the reconfiguring of cross connection unit, andsaid at least two processor units from said plurality of processor units and enabling reconfigurably linking one processor unit to another processor unit, and of enabling collective fetching and branch prediction; a second cross unit connection component reconfigurably and operatively connected to said at least two processor units from said plurality of processor units, said second cross unit connection component enabling steering and renaming instructions for/from each processor unit;a third cross unit connection component reconfigurably and operatively connecting said at least two processor units from said plurality of processor units and enabling transfer of output instruction values from one processor unit as input instruction values to another processor unit;a fourth cross unit connection component reconfigurably and operatively connecting at least two processor units from said plurality of processor units, said fourth cross unit connection component enabling transferring signals between reorder buffer memories in processor units from said plurality of processor units, and of enabling collective instruction commit.a fetch management component operatively connected to said first cross unit connection component, said fetch management component enabling coordinating distributed operation of fetch components in each processor unit.a steering management component enabling steering and renaming instructions for/from each processor unit; and said steering management component being operatively connected to each processor unit through said second cross unit connection component.6.

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    responsible for their marriages ending, and the mothers-in-law get most of the blame.